This invention relates to CMOS circuits, and more particularly to techniques for maintaining a constant slew rate within a CMOS circuit.
Complementary metal oxide semiconductor (CMOS) circuits are subject to a slew rate that typically varies with environmental conditions and/or process parameters. A slew rate that varies over a large range is typically undesirable for many applications such as an Ethernet line driver. Therefore, CMOS circuits are typically modified to maintain a substantially constant slew rate.
Many techniques have been employed to maintain a substantially constant slew rate. A few of these techniques include trimming the circuit with fuses, the use of an oversampled waveform synthesizer, or using a replica bias circuit that is slaved to a phase locked loop. However, each of the previous techniques has disadvantages including, but not limited to, increasing the complexity of the circuit and having a corresponding increase in manufacturing cost.
Each transistor that is fabricated on the same integrated circuit chip typically has similar switching characteristics and behavior. This results from all of the devices on the same chip being fabricated at the same time with the same process parameters. As such, the circuits operate in a matched manner over wide variations in power supply voltage, process parameters (threshold voltage, channel length, etc.), and temperature. This consistent behavior allows the circuit of the present invention to control the relative current flow as will be described below.